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Intel 12th gen “Alder Lake-S” desktop CPU spotted in SiSoftware database, sporting 16 cores and DDR5 memory

Some new details have surfaced regarding Intel’s future next-gen 12th generation of Alder Lake-S Core processor lineup. As you may already know by now that Alder Lake-S Core processors are said to be the company’s first 10nm SuperFin-based mainstream desktop SKUs. We have also seen several documents, datasheets, and release notes for these CPUs which have also appeared on Intel’s own developer website as well.

The 10 nm Enhanced SuperFin process technology was originally designed for datacenter/HPC market segment and its products in mind, to provide enhancements to the power delivery system, MEOL and BEOL etc, in semiconductor terms.

These CPUs will leverage the high-velocity PCIe 5.0 interface, and support for DDR5 memory. Alder Lake CPU lineup will bring the concept of heterogeneous multi-core to x86 processors for consumer and client PCs. These processors would thus feature a total of 16 cores in a single package, at least initially.

Alder Lake-S CPU lineup will be the first Intel architecture to offer ARM’s big.LITTLE approach to desktop processors. These processors have been confirmed to support a new LGA1700 socket. For more technical details please kindly refer to this article.

Now, renowned Hardware leaker @momomo_us has recently spotted some entries for Intel’s Alder Lake-S CPU within the SiSoftware database. One Alder Lake-S processor sample was already discovered in the SiSoftware website before. Back in December 2020, another Alder Lake CPU sample appeared in the Geekbench database as well.

The processor seems to be an early engineering sample, and sports the same 16-core, 32-thread configuration as an early sample that appeared back in October. The SiSoftware database entry showcases a prototype having 16 cores and 32 threads running at a base frequency of 1.8 GHz and a boost speed of 4 GHz higher than the previously leaked sample.

There is also 12.5 MB of L2 cache on board, which has been split into 10 pairs of 1.25 MB, and a total of 30 MB of level-three (L3) cache.

SiSoftware detects the Alder Lake-S as a 16-core SKU, meaning that there are eight Golden Cove cores and eight Gracemont cores onboard this chip. This coincides with the previous configuration in which it was rumored that Alder Lake-S would feature an 8+8 core configuration, where half the cores are going to be BIG Cores and the remaining would be small Cores.

These architectures are Golden Cove (Willow Cove successor) and Gracemont (Tremont successor), respectively. Willow Cove is expected to appear in the upcoming 11th gen Rocket Lake-S series of processors.

However, the software incorrectly mentions that the number of threads is 32, because in Alder Lake S lineup hybrid design, only the high-performance cores (aka big cores) are expected to support hyper-threading. Assuming the bigger cores will feature multi-threading, we get a total of 8 cores and 16 threads.

The smaller cores on the other hand, however won’t feature SMT and will be configured at 8 cores and 8 threads. This gives us a total of 16 cores and 24 threads, but we can’t say for sure whether this would indeed be Alder Lake’s actual hybrid configuration.

It’s also plausible that the SiSoftware’s benchmark software isn’t yet fully optimized for Alder Lake-S, and there in no way the clock speeds for the chip are final as well. But it will be interesting to see how clock speeds are managed between the two core architectures, Golden Cove and Gracemont cores.

Intel Alder Lake-S desktop CPU SiSoftware-1

The sample also sports a 32 EU Xe iGPU on board the die which features a total of 256 stream processors for the graphics. The graphics chip seems to be clocked at 1500 MHz and is based on the newer Gen 12.2 architecture.

An internal Alder Lake test platform was used for this sample, showing support for up to DDR5-4800 memory. This confirms that Alder Lake will be the first Intel desktop platform to leverage the DDR5 memory standard, and a new motherboard chipset and socket called LGA 1700.

Intel Alder Lake-S desktop CPU SiSoftware-2Intel Alder Lake-S desktop CPU SiSoftware-3

What’s surprising here is that the previous 1.4 GHz Alder Lake-S chip actually delivered almost 21% higher score on the processor multi-media test than this new 1.8 GHz sample. Multi-media performance has dropped from 318.86 Mpix to 263.46 Mpix.

However, the memory bandwidth has increased from 13.49 GB/s to 34.21 GB/s, an improvement of up to 154% in the test. But this is because the previous Alder Lake-S sample was paired with a DDR4 memory, while this new sample runs with DDR5 memory. The summarized GPU score also sees an improvement up to 38.6% on this new 1.8 GHz sample.

As per one old coreboot leaked code, spotted by @davideneco25320 back in August 2020, the full configuration of the Alder Lake series of CPUs, namely the CPU, GPU and the PCH was detailed to some extent. It appears we would be getting several Alder Lake CPU variants, in the Alder Lake S and P-Series configurations. This can get a bit confusing though because of the “segmentation”.

For example, the reported config numbers ‘8+8+1’ actually refer to the BIG, SMALL, and GPU core counts respectively. So we assume all variants will indeed have the Small cores on desktop as well. So expect a maximum of 2 to 8 big cores, and up to 0 to 8 small cores.

Some internal codenames for the Platform Controller Hub (PCH) were also leaked before. It seems that Intel will use four PCHs with distinct features to cater to different market segments. These appear to be the Base, Mainstream, Premium and the Super Tier platforms.

  • { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_0, “Alderlake-P-Base SKU” },
  • { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_1, “Alderlake-P-Super SKU” },
  • { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_2, “Alderlake-P Premium SKU” },
  • { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_3, “Alderlake-P Mainstream SKU” },
  • { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_4, “Alderlake-P-Base SKU” },
  • { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_5, “Alderlake-P-Base SKU” },
  • { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_6, “Alderlake-P Super SKU” },
  • { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_7, “Alderlake-P Premium SKU” },
  • { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_8, “Alderlake-P-Base SKU” },
  • […]
  • { PCI_DEVICE_ID_INTEL_ADP_S_ESPI_0, “Alderlake-S-Base SKU” },
  • { PCI_DEVICE_ID_INTEL_ADP_S_ESPI_1, “Alderlake-S-Super SKU” },
  • { PCI_DEVICE_ID_INTEL_ADP_S_ESPI_2, “Alderlake-S Premium SKU” },
  • { PCI_DEVICE_ID_INTEL_ADP_S_ESPI_3, “Alderlake-S Mainstream SKU” },
  • { PCI_DEVICE_ID_INTEL_ADP_S_ESPI_4, “Alderlake-S-Base SKU” },
  • { PCI_DEVICE_ID_INTEL_ADP_S_ESPI_5, “Alderlake-S-Base SKU” },
  • { PCI_DEVICE_ID_INTEL_ADP_S_ESPI_6, “Alderlake-S Super SKU” },
  • { PCI_DEVICE_ID_INTEL_ADP_S_ESPI_7, “Alderlake-S Premium SKU” },
  • { PCI_DEVICE_ID_INTEL_ADP_S_ESPI_8, “Alderlake-S-Base SKU” }

Just to recap some of the previous findings/leaks on Alder Lake Platform specs.

Back in July, a new GNU compiler update was posted by Phoronix, which included a list of compatible instructions for both Intel’s upcoming data center/HPC Sapphire Rapids chips and the Alder Lake desktop chips.

According to the GNU update Alder Lake-S CPU lineup was noticeably missing full support for the AVX-512, a SIMD instruction recently introduced by Intel for its desktop chips.

These instruction sets are also disabled in Intel’s latest hybrid Lakefield chips. This is done to keep the instruction set more consistent between cores (small Atom Tremont cores lack support for AVX instructions though). This also eases the operating system scheduling routines that target different workloads at the corresponding cores.

Therefore, the lack of AVX-512 support for Alder Lake-S serves as further evidence that Intel will bring a new hybrid core architecture design to desktop PCs.

However, it should be noted that while the lack of AVX-512 support hints at a hybrid design, the Alder Lake ‘support matrix’ has a listing of standard AVX instructions that are not supported by the current generation Atom Tremont cores. So this means that the next generation of Atom Gracemont cores, which are largely considered ‘small’ cores used in Alder Lake, could bring AVX support, albeit in a limited manner.

The Sapphire Rapids chips on the other hand support many AVX instructions, like for example AVX512F, CLWB, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VNNI, and the new AVX512BF16 that enables support for bfloat 16, which is a compact numerical format having similar performance to FP32, but with only half the bits.

The Alder Lake-S CPU architecture will also feature the CLDEMOTE ‘cache line demote instruction’ set, which I’ve explained in my previous article. Though, to reiterate, the CLDEMOTE instruction hints to hardware that the cache line that contains the linear address should be moved (demoted) from the cache(s) closest to the processor core to a level more distant from the processor core.

CLDEMOTE instructions are used so that the OS can tell the processor core which specific line in the cache is no longer needed, and its contents can be moved elsewhere, however, not directly into the main operating memory, but still into the processor cache, at higher levels (from L1 to L2 and from L2 to L3).

Also, according to one recent report posted by Zhihu, the new hybrid Technology in the upcoming Alder Lake architecture would allow both CPU cores (small and big) to share the same instruction set and registers, but the actual availability of certain instructions would depend on which core is actually enabled and active.

The user also shared a screenshot from Intel’s internal document which suggests that the following AVX-512, TSX-NI, and the FP16 instruction sets will be disabled when the Hybrid Technology is enabled (both Big and Small cores are enabled at the same time).

The instructions will only work when the hybrid technology is disabled, which means the Small cores are disabled. By disabled we can think of the processor’s mode/PL state, though I need more technical info to confirm how this will work on desktop PCs.

Both the big and small cores will have the same amount of instruction sets and model-specific registers, but will have different computational powers, and the overhead will also differ.

We can assume the big cores to have higher throughput and clock speeds, whereas the small cores are going to be more power efficient. Like mentioned before, the following instruction sets, e.g. AVX512, Intel TSX and FP16, are only going to work on the Big cores. ARM’s Big/Small core architecture makes more sense for mobile devices, to conserve power, but we still don’t know how this Hybrid technology is going to actually work on desktops.

Intel has not announced any exact launch date for Alder Lake-S processors yet, but since the Alder Lake-S is the successor to Tiger Lake, so the processors will debut as the 12th Generation Core lineup next year, in the second half of 2021.

Stay tuned for more tech news!