AMD’s Martin Hilgeman has revealed some early details about the Zen 3 architecture at the HPC AI Advisory Council’s 2019 UK Conference. Moreover, Hilgeman confirmed that Zen 4 is currently in a design phase.
According to Hilgeman, Zen 3 server CPUs will release on AMD’s existing SP3 server socket, will support DDR4 memory and offer the same TDP. In addition, they will offer the same core count as the ROME server CPUs. Now while Hilgeman was talking only about the server processors, we can assume that the same will apply to the desktop processors too.
Hilgeman also confirmed that Zen 3 would move away from Zen/Zen 2’s split cache design. AMD’s previous Zen CPUs split the L3 cache between two quad-core CCXs. Theoretically, this could mean that Zen 3 may offer a larger, combine L3 cache. This could benefit the CPU from granting all CPU cores better cache access. Furthermore, AMD may also increase the cache capacity.
Again, in theory this could lower some internal CPU latencies, and allow Zen 3 processors to cache more data on-die. These changes could be beneficial for Zen 3’s gaming performance, given AMD’s existing marketing for “GameCache”, and its benefits for Zen 2.
Lastly, we can assume that AMD will further improve the IPC on Zen 3. After all, we already know that Intel aims to improve the IPC on its next-generation CPUs. As such, it will be interesting to see whether the red team will be able to further close its gap.
Kudos to our reader ‘Metal Messiah’ for bringing this to our attention.