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Intel’s Alder Lake-S and Alder Lake-P CPU lineup’s full configurations have been leaked, CPU, GPU and PCH info

Back in July, Intel confirmed that its next-gen 10nm ‘Alder Lake’ CPU lineup will launch in the second half of 2021. Intel has also confirmed that the next-gen Alder Lake-S CPUs will use a new Hybrid Core/Atom processor architecture.

Intel’s next generation of Alder Lake-S Core processors are said to be the company’s first 10nm-based mainstream desktop processors, and we have already seen documents, datasheets, and release notes for these CPUs which also appeared on Intel’s own developer website. These processors have been confirmed to support a new LGA1700 socket. These next-gen CPUs are also expected to support the DDR5 memory and PCIe 4.0 interface. As the name implies, the LGA1700 socket is comprised of 1,700 pins, which gives us 500 more pins that the existing LGA1200 socket that houses Comet Lake-S and the upcoming Rocket Lake-S series of processors.

The new LGA1700 socket will have support for at least 3 generations of Intel CPUs. This is something new for Intel because the company has been known to support a short socket lifespan till now. These latest new findings indicate that Intel’s LGA1700 socket will compete with AMD’s AM5 socket in terms of platform longevity.

Alder Lake-S CPU lineup will be the first Intel architecture to offer ARM’s big.LITTLE approach to desktop processors. Alder Lake-S would feature an 8+8 core configuration, in which half the cores are going to be ‘Big Cores’ and the rest of the remaining would be ‘Small Cores’. These processors would thus feature a total of 16 cores in a single package. According to one report these architectures are Golden Cove (Willow Cove successor) and Gracement (Tremont successor), respectively. Willow Cove is expected to appear in the upcoming Rocket Lake-S series of processors.

Now, according to a new leak coming from Coreboot, via @davideneco25320, we get to know about the full configuration of the Alder Lake series of CPUs, namely the CPU, GPU and the PCH info. Few months back, it was reported that Alder Lake-S will be available in three combinations. For example, the reported config numbers ‘8+8+1’ actually refer to the BIG, SMALL, and GPU core counts respectively. The latest report from Coreboot gives us some useful info regarding the Alder Lake-S (desktop) and Alder Lake-P (mobile, but here is some speculation going around that Alder Lake-P could be Intel’s Atom P-series.) series of CPUs. As evident from that coreboot patch report, the Alder Lake series will indeed feature 2 to 8 big cores, and 0 to 8 small cores, respectively.

The entry-level Alder lake-S SKUs are going to stick with a dual-core and quad-core design/configuration, with no ‘small’ cores. On the other hand, the chips with six and eight big cores can come with two, four, six or eight small cores. The flagship Alder Lake-S processor features eight big cores and eight small cores, according to the coreboot report. When it comes to Alder Lake-P, Intel may keep it simple. The entry-level Alder Lake-P chip will reportedly come with just two big cores, with the flagship maxing out at six big cores and eight small cores. It appears that Alder Lake-P is listed with two GPU cores, the GT2 iGPU. This could also mean that ‘Alder Lake-P’ will carry more integrated graphical performance/power than the standard Alder Lake-S series of processors.

Coming to the igpu/integrated graphics, the Alder Lake Core S-Series are only going to feature the GT1 configuration. GT2 which is a higher-end configuration will launch with some of the P-Series SKUs, although the majority of the models are still going to feature GT1. We don’t know if the integrated graphics is based on the same Gen12 XE Graphics as Rocket Lake, or whether it will use a totally new architecture. The same Coreboot leak also reveals the internal codenames for the Platform Controller Hub (PCH). It seems that Intel will use four PCHs with distinct features to cater to different market segments. These appear to be Base, Mainstream, Premium and the Super Tier.

Back In July, a new GNU compiler update was posted by Phoronix, which included a list of compatible instructions for both Intel’s upcoming data center/HPC Sapphire Rapids chips and the Alder Lake desktop chips, with Alder Lake noticeably missing support for AVX-512, a SIMD instruction recently introduced by Intel for its desktop chips. These instruction sets are also disabled in Intel’s latest hybrid Lakefield chips. This is done to keep the instruction set more consistent between cores (small Atom Tremont cores lack support for AVX instructions though). This also eases the operating system scheduling routines that target different workloads at the corresponding cores. Therefore, the lack of AVX-512 support for Alder Lake-S serves as further evidence that Intel will bring a new hybrid core architecture design to desktop PCs.

However, it should be noted that while the lack of AVX-512 support hints at a hybrid design, the Alder Lake ‘support matrix’ has a listing of standard AVX instructions that are not supported by the current generation Atom Tremont cores. So this means that the next generation of Atom Gracemont cores, which are largely considered ‘small’ cores used in Alder Lake, could bring AVX support, albeit in a limited manner. The Sapphire Rapids chips on the other hand support many AVX instructions, like for example AVX512F, CLWB, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VNNI, and the new AVX512BF16 that enables support for bfloat 16, which is a compact numerical format having similar performance to FP32, but with only half the bits.

The Alder Lake-S CPU architecture will also feature the CLDEMOTE ‘cache line demote instruction’ set, which I’ve explained in details in my previous article. Though, to reiterate, the CLDEMOTE instruction hints to hardware that the cache line that contains the linear address should be moved (demoted) from the cache(s) closest to the processor core to a level more distant from the processor core. CLDEMOTE instructions are used so that the OS can tell the processor core which specific line in the cache is no longer needed, and its contents can be moved elsewhere, however, not directly into the main operating memory, but still into the processor cache, at higher levels (from L1 to L2 and from L2 to L3).

These processors are expected to feature next-gen XE Graphics (Gen12 and above). Since the iGPU of Alder Lake-S seemingly has more cores than the current ‘Comet Lake-S’ CPU lineup, we can expect better performance out of these chips.

Also, according to one recent report posted by Zhihu, the new hybrid Technology in the upcoming Alder Lake architecture would allow both CPU cores (small and big) to share the same instruction set and registers, but the availability of certain instructions would depend on which core is actually enabled and active.

The user also shared a screenshot from Intel’s internal document which suggests that the following AVX-512, TSX-NI, and FP16 instructions will be disabled when the Hybrid Technology is enabled (both Big and Small cores are enabled at the same time). The instructions will only work when the hybrid technology is disabled, which means the ‘Small’ cores are disabled. By disabled we can think of the processor’s mode/PL state, though I need more technical info to confirm how this will work on Desktop PCs.

Both the big and small cores will have the same instruction sets and model-specific registers, but will have different computational powers, and the overhead will also differ. We can assume the big cores to have higher throughput and clock speeds, whereas the small cores are going to be more power efficient. Like mentioned above, the following instruction sets AVX512Intel TSX and FP16, are only going to work on the Big cores. The ARM’s Big/Small core architecture makes more sense for mobile devices, to conserve power, but we still don’t know how this Hybrid technology is going to work on Desktops.

Intel Alder Lake S and P-Series configurations can be seen in the following chart. This can get a bit confusing though, honestly speaking, because of segmentation.

Intel Alder Lake-S and Alder Lake-P CPU lineup

And these are the Intel Alder Lake PCH codenames:

  • { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_0, “Alderlake-P-Base SKU” },
  • { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_1, “Alderlake-P-Super SKU” },
  • { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_2, “Alderlake-P Premium SKU” },
  • { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_3, “Alderlake-P Mainstream SKU” },
  • { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_4, “Alderlake-P-Base SKU” },
  • { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_5, “Alderlake-P-Base SKU” },
  • { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_6, “Alderlake-P Super SKU” },
  • { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_7, “Alderlake-P Premium SKU” },
  • { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_8, “Alderlake-P-Base SKU” },
  • […]
  • { PCI_DEVICE_ID_INTEL_ADP_S_ESPI_0, “Alderlake-S-Base SKU” },
  • { PCI_DEVICE_ID_INTEL_ADP_S_ESPI_1, “Alderlake-S-Super SKU” },
  • { PCI_DEVICE_ID_INTEL_ADP_S_ESPI_2, “Alderlake-S Premium SKU” },
  • { PCI_DEVICE_ID_INTEL_ADP_S_ESPI_3, “Alderlake-S Mainstream SKU” },
  • { PCI_DEVICE_ID_INTEL_ADP_S_ESPI_4, “Alderlake-S-Base SKU” },
  • { PCI_DEVICE_ID_INTEL_ADP_S_ESPI_5, “Alderlake-S-Base SKU” },
  • { PCI_DEVICE_ID_INTEL_ADP_S_ESPI_6, “Alderlake-S Super SKU” },
  • { PCI_DEVICE_ID_INTEL_ADP_S_ESPI_7, “Alderlake-S Premium SKU” },
  • { PCI_DEVICE_ID_INTEL_ADP_S_ESPI_8, “Alderlake-S-Base SKU” }