Intel’s next generation of Alder Lake-S Core processors are said to be the company’s first 10nm mainstream desktop processors, and we have already seen documents, datasheets, and release notes for these CPUs which also appeared on Intel’s own developer website. These processors have been confirmed to support a new LGA1700 socket.
Alder Lake-S will be the first Intel architecture to offer ARM’s big.LITTLE approach to desktop processors. These next-gen CPUs are also expected to support the DDR5 memory and PCIe 4.0 interface. The LGA1700 socket will have support for at least three generations of Intel CPUs. I’ve talked about Alder Lake CPUs before in my previous articles as well. According to previous documents, these new chips have been confirmed to support a new Hybrid Architecture, aka ‘big core/small core’ design.
Now, a new recent leak coming from the SiSoftware website as spotted by @TUM_APISAK, reveals the specs of the Alder Lake’s integrated graphics/iGPU. It appears that Intel’s team might be evaluating the performance of the upcoming 12th Gen Core Alder Lake-S lineup. The iGPU has been spotted with 32 EUs, which translates to 256 Shadings Units. For comparison, the flagship Core i9-10900K CPU ships with 24 EUs (i.e. 192 Shading Units, on the UHD630). So next-gen Intel processors are going to pack more iGPU cores.
These processors are expected to feature next-gen XE Graphics (Gen12 and above). Since the iGPU of Alder Lake-S seemingly has more cores, we can expect better performance out of these chips.
According to one recent post by Zhihu, the new hybrid Technology in Alder Lake architecture would allow both CPU cores (small and big) to share the same instruction set and registers, but the availability of certain instructions would depend on which core is actually enabled and active. The user shared a screenshot from Intel’s internal document which suggests that the following AVX-512, TSX-NI, and FP16 instructions will be disabled when the Hybrid Technology is enabled (both Big and Small cores are enabled at the same time).
The instructions will only work when the technology is disabled, which means the ‘Small’ cores are disabled. By disabled we can think of the processor’s mode/PL state, though I need more technical info to confirm how this will work on Desktop PCs.
Both the big and small cores will have the same instruction sets and model-specific registers, but will have different computational powers, and the overhead will also differ. We can assume the big cores to have higher throughput and clock speeds, whereas the small cores are going to be more power efficient. Like mentioned above, the following instruction sets AVX512, Intel TSX and FP16, are only going to work on the Big cores. The ARM’s Big/Small core architecture makes more sense for mobile devices, to conserve power, but we still don’t know how this Hybrid technology is going to work on Desktops.